In recent years, with progress of miniaturization of semiconductor devices, the semiconductor devices have come to require finer processing than the current highest resolution level of the photolithography technique, and such finer processing has become more difficult. In this respect, sidewall processing and double exposure are used to form the wirings in such semiconductor devices. The sidewall processing, however, cannot be used in forming contact holes while the double-exposure method is not very preferable in view of the cost. Consequently, stable formation of contacts has become more difficult.
In NAND flash memories, for example, the upper portion of the silicon substrate is divided by STIs (Shallow Trench Isolations) into plural line-shaped active areas extended in one direction. Then, multiple memory transistors of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) structure are formed along the active areas. The active areas are supplied with electric potentials via bit-line contacts from the bit lines formed in an upper layer (for instance, refer to JP-A Hei 7-202143 (Kokai)). In such NAND flash memories, the active areas are arranged at a smaller pitch to pursue higher integration of memory transistors. This arrangement, however, makes a distance between every two adjacent bit-line contacts so small that the bit-line contacts cannot be formed stably.